1. Field of the Invention
The present invention relates to a wiring structure in which a wiring portion and a plug portion are formed integrally, and a method of forming the same. The invention is particularly suitable to damascene wiring formed by filing a wiring groove made in an insulating film with a metal material.
2. Description of the Related Art
To meet the high integration of a semiconductor device and a reduction in chip size in recent years, not only the miniaturization of wiring, but also multi-layer wiring is being promoted at an increasing fast rate. With a logic device having such multi-layer wiring, a wiring delay is becoming one of dominant factors causing a device signal delay. A signal delay in the device is proportional to the product of wiring resistance and a wiring capacity, and a reduction of wiring resistance and wiring capacity becomes an issue of great importance to improve the wiring delay.
In order to reduce the wiring resistance, there has been proposed a technique of forming Cu wiring so as to fill up a wiring groove made in an insulating film through the so-called damascene method. Further, in order to reduce the wiring capacity, the use of an organic low dielectric material based on aryl ether or a low dielectric material based on fluorocarbon for the insulating film instead of conventionally used SiO2 has been examined. These materials have a dielectric constant of 2.3 to 2.5, which is approximately 40% to 55% lower than that of the conventional insulation materials, such as SiO2, SiN, and SiON. It is expected that combining a low dielectric film with Cu wiring particularly in a global wiring portion, which is assumed to have a large influence upon the wiring delay, will make a significant contribution to improvement of the device performance.
However, the conventional damascene method has the following problem when a SiO2 film used as the insulating film for the Cu wiring is replaced with a low dielectric film.
That is, in general, a low dielectric material achieves a low dielectric constant by lowering the film density. Hence, a low dielectric film has low heat conductivity and poor mechanical strength in comparison with the SiO2 film. On the other hand, in order to meet the advancement of technology, it is general to improve the device performance of the logic device by increasing the allowable current density. An increase in allowable current density means an increase in Joule heat generated when a current flows through the wiring portion, and how efficiently the heat generated from Joule heat is released to a silicon substrate becomes a big problem as the technology advances further. This problem, in particular, becomes serious when a low dielectric material having small heat conductivity is used.
Further, when a low dielectric film having poor mechanical strength is used as the insulating film, there is a problem that film separation or cracking occurs in the dicing process or wire bonding process following the wafer process due to application of considerably large shear stress, compressive stress, or tensile stress.